This invention relates to a pulse amplifier circuit and, more particularly, to a push-pull pulse amplifier using field effect transistors and wherein a power loss to the load caused by simultaneous conduction of the field effect transistors is substantially eliminated.
Push-pull amplifier configurations are advantageous in that higher power levels can be obtained therefrom with minimal distortion. Hence, push-pull power amplifiers find ready application in audio equipment. In one type of push-pull amplifier, field effect transistors (hereinafter FET' s) are used as the amplifying elements because FET's generally exhibit switching characteristics which are improved over bipolar transistors. However, inter-electrode capacitance, particularly gate-source capacitance and gate-drain capacitance, of an FET may, in many instances, be detrimental to the overall operation of the FET push-pull amplifier.
The aforementioned inter-electrode capacitance is particularly noticeable when pulse signals are supplied to the gate electrode of the FET, and such capacitance may be considered to be the inherent input capacitance of the FET which is present at its gate electrode. This input gate capacitance cooperates with the resistance of the drive circuit which is coupled to the gate electrode of the FET so as to form an RC delay circuit. This means that the amplified pulse signal produced by the FET exhibits sloping or rounded flanks. That is, the time constant of the RC delay circuit imparts a significant delay to the pulse signal which is supplied to the FET gate electrode, thereby delaying the positive and negative transitions (i.e. the rise time and fall time) of the amplified pulse. This distortion is undesirable and can result in a deteriorated or degraded output.
When a depletion-type FET, such as a junction FET, and particularly a vertical channel junction FET, is used in a switching mode in the aforementioned push-pull pulse amplifier, this FET is more highly conductive when its gate-source voltage V.sub.GS is zero. With this zero gate-source voltage, the FET may be considered to be ON, and its drain-source voltage V.sub.DS is substantially zero. The FET is rendered non-conductive, that is, it is turned OFF, when its gate-source voltage increases to the FET pinch-off voltage. When the FET is OFF, its drain-source voltage is a maximum value, and if the FET is connected such that its drain-source circuit is connected in series with a DC supply voltage, this drain-source voltage will be substantially equal to that DC supply voltage. Because of the aforementioned RC time constant attributed to the input capacitance of the FET and the resistance of the drive circuits connected thereto, if the voltage which is applied to the gate electrode of the FET changes abruptly from a zero level to the pinch-off level, the FET will not be turned OFF immediately. Rather, a time delay is encountered until the FET is OFF. Similarly, if the voltage which is applied to the gate electrode changes abruptly from the pinch-off level to the zero level, the FET will not be turned ON until after a time delay. Hence, the ideal linear relation between drain-source voltage V.sub.DS and gate-source voltage V.sub.GS will not be attained. Rather, a change in V.sub.GS is delayed with respect to a change in V.sub.DS, thereby appearing as a non-linear relationship. Consequently, when these FET's are used in a push-pull pulse amplifier, the delay encountered in turning OFF one FET while turning ON the other means that there will be some overlap in time during which both FET's are ON. Hence, a portion of the current which otherwise would flow to the load which is driven by the FET's will be diverted so as to flow through the FET which is in the process of turning OFF. This means that a portion of the input power for driving the load is lost to the FET which should be OFF but, because of its turn-off time delay, is still ON.
The problem of turn-on and turn-off delay also is encountered in bipolar transistors. When a bipolar transistor is in saturation, the minority-carrier density stored in the base region is relatively high. In order for the transistor to be operated in its switching mode, this abnormal carrier density first must be removed before the transistor can be turned OFF. Hence, a relatively long delay may elapse before the bipolar transistor responds to a turn-off signal applied thereto. It has been proposed (Japanese Patent Publication No. 5113/64, published Apr. 21, 1964) to provide a separate minority carrier discharge circuit which is actuated when the bipolar transistor is to be turned OFF. This circuit consists of a diode which is connected to the transistor base electrode and which is poled in a direction such that when the diode is forward biased, the minority carriers may be discharged therethrough. However, this known prior art is not concerned with the problem of overlap in the ON states of transistors which are connected in push-pull relation. Hence, this prior art does not recognize the defect of power loss that may be caused by such ON-state overlap in push-pull transistors. Furthermore, although there is a turn-off delay in bipolar transistors caused by abnormally high minority current densities in the base region when the transistor is in saturation, there is no comparable turn-on delay. This differs from an FET wherein the gate input capacitance thereof causes both a turn-on and a turn-off time delay.
Although the existence of input gate capacitance of an FET has been known, there appears to have been no proposal to utilize this capacitance so as to avoid the problem of power loss mentioned above. Generally, the input gate capacitance of an FET is substantially independent of bias current and, therefore, cannot be easily controlled (i.e., minimized) by judicious selection of the bias current. Nevertheless, it has been known that the time constant of the input gate capacitance and the drive circuit resistance affects the turn-off time of the FET. In the text "FET Applications Handbook" by Eimbinder, Tab Books (1970), it is noted that when a turn-off signal is applied to an FET, an excess charge is provided on the stray capacitance and this charge must be eliminated and the capacitance recharged to supply potential before the FET can be considered OFF. The time required to eliminate the excess charge is the turn-off delay. This text also recognizes that a turn-on delay is caused by the requirement to discharge the gate-source capacitance before the FET can turn ON. However, this text notes that the rise time of the circuit, that is, the turn-on time, is much faster than the fall time, that is, the turn-off time. To account for this turn-off delay, a diode is connected to the gate electrode of the FET and is reverse biased when the FET is to be turned ON, while being forward biased to turn the FET OFF. A capacitor is in parallel with the diode to provide a discharge current path for the input gate capacitance of the FET. Even though these turn-on and turn-off delays are recognized, the problem of power loss is not. In fact, this text states that when two FET's are used to drive a single load in a multiplex type of application, it is advantageous to provide some overlap during which both FET's are ON. Accordingly, the turn-off time should be at least as long as the turn-on delay in order to assure this overlap. See Chapter 17 and particularly Sections 17-3 and 17-9 of this text.